This nothing like my usual pages.

It is just a place I've posted two diagrams relating to the von Neumann et al computer build at the Institute for Advanced Studies, in Princeton. I am baffled!...

NOTE: The diagrams are marked "No.7"... they were "there", at the IAS, while the computer was being built. I don't know that they represent the final, working design for the shift register! (RegisterS?).... but by "No. 7", you'd think they would have had something that "should" have worked. I can't see how the circuit could, though... and would like to!

What I THINK is true so far...

I can 'read' both versions. I know what the 'building blocks' are, and how they work.

I think the building blocks are simple little SR latches (often wrongly called flip-flops). Only two inputs, two outputs per latch. I know what the circuit as a whole accomplishes... it is a "shift register".

See Wikipedia for info on SR latches and shift registers. I THINK all of this was done with LEVEL sensitive elements, not EDGE sensitive ones. I think the diagram shows only a part of the whole register. (Slightly different fractions of the whole, in the two diagrams, I think you'll agree.) I think "stuff" went in at one end... (or maybe either end.) I don't believe there was a clock signal.

I think this shift register worked by Set (S) and (R) lines working as follows: Both would normally be high. To put 4 bits in the register, the R line would go low, then high, four times. If that's ALL that happened, there would be four zeros in the register. If, shortly after the R line went high after the second low-then-high, then the register would hold 0100 (or 0010, depending on how you look at it!)

Possibly a huge, unhelpful distraction... As I say, I think the IAS shift register had no shared clock signal. But, for what it is worth, an article titled 'Building a 4-bit shift register from 7400 NAND gates' shows how a gated D-latch can be built from an SR latch, and how ONE SORT of shift register can be built from gated D latches.

Diagram of circuit of Shift Register ('Shifting register') in IAS computer

Diagram of circuit of Shift Register ('Shifting register') in IAS computer

My "grasp" of the circuit so far... (I may have mis-understood... don't be put off by my thoughts!)

Annotated diagram of circuit of Shift Register ('Shifting register') in IAS computer

My guess? (If the above is even close to right.. and this may be "right", but "backward". I'm assuming that the bit flow through the register from left to right.)...

CellIn0 is where data is fed into the shift register.

CellOut1 is where it comes out.

CellOut1 is the input for the clock signal that drives everything.

CellOut0 would matter as the input to the next cell to the left, inside the register. (The diagram showing just a 2 bit register). And it would either be surplus to requirements, or the signal for timing the loop, where it came out from the left-most cell.

And the shift process to load the register with some data would(?) be as follows...


Preset a bit on CellIn0

Wait for the voltage to stabilize.

Take CellIn1 high, then low, then high. (Or would it be the other way around, for the valve circuit shown?)

Wait for that pulse to work it's way through the register.

Until sufficient bits have been "fed into" the register.

If that much right,,, on to a modern implementation, using NANDs, etc, but trying to stay as close to the above as possible. (I will probably shirk the "joys" of doing it in transistors... but a circuit for the same would be of interest, either as a simple sketch, or in KiCad? (Only send one if you are happy to have your work published, copyright released. And tell me how you would like that credited.)

Thoughts, contributions welcome. I will pay for follow-up phone calls.Contact details.